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philips semiconductors gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator product data supersedes data of 2003 dec 18 2004 jun 21 integrated circuits
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2 2004 jun 21 features ? operates as a gtl/gtl/gtl+ to lvttl sampling receiver or lvttl to gtl/gtl/gtl+ driver ? 3.0 v to 3.6 v operation ? lvttl i/o not 5 v tolerant ? series termination on the lvttl outputs of 30 w ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 250 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 500 ma ? package offered: tssop28 description the gtl2006 is a 13-bit translator to interface between the 3.3 v lvttl chip set i/o and the xeon ? processor gtl/gtl/gtl+ i/o. the gtl2006 is designed for platform health management in dual processor applications. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 13 16 14 15 v ref 1ao 2ao 5a 6a 8ai 11bi 11a 9bi 3ao 4ao 10ai1 10ai2 gnd 9ao 10bo2 10boi 4bi 3bi 6bi 5bi 11bo 8bo 7bo2 7bo1 2bi 1bi v cc sw01091 figure 1. pin configuration pin description pin number symbol name and function 1 v ref gtl reference voltage 26, 8, 1013, 15 nan data inputs/outputs (lvttl) 7, 9, 16, 1727 nbn data inputs/outputs (gtl/gtl/gtl+) 14 gnd ground (0 v) 28 v cc positive supply voltage quick reference data typical symbol parameter conditions typical unit symbol parameter conditions t amb = 25 c b to a a to b unit t plh t phl propagation delay an to bn or bn to an c l = 50 pf; v cc = 3.3 v 5.5 5.5 ns c i/o i/o pin capacitance outputs disabled; v i/o = 0 v or 3.0 v 7.8 4.5 pf ordering information packages temperature range order code topside mark dwg number 28-pin plastic tssop 40 c to +85 c GTL2006PW gtl2006 sot361-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 3 function tables input output 1bi/2bi/3bi/4bi/9bi 1ao/2ao/3ao/4ao/9ao l l h h input output 8ai 8bo l l h h input input output 10ai1/10ai2 9bi 10bo1/10bo2 l l l l h l h l l h h h input input/output output 5bi/6bi 5a/6a (open drain) 7bo1/7bo2 l l h 1 h l 2 l h h h input input/output output 11bi 11a (open drain) 11bo l h l l l 2 h h l h h = high voltage level l = low voltage level notes: 1. the enable on 7bo1/7bo2 include a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. 2. open drain input/output terminal is driven to logic low state by other driver.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 4 logic symbol sw01092 gtl v ref 2bi 1bi 10ai1 10ai2 gtl input 11bi 11bo 10bo2 10bo1 4ao 3ao 2ao 1ao lvttl i/o gtl outputs gtl inputs 5bi lvttl i/o 11a (open drain) 5a (open drain) 6a (open drain) lvttl inputs 7bo1 1 2 3 4 5 6 26 25 24 22 21 20 19 18 17 16 15 8 9 10 11 12 13 gtl2006 27 lvttl input 8ai gtl input 9bi lvttl outputs 7bo2 6bi 8bo 23 3bi 4bi 9ao lvttl output 7 gtl outputs gtl inputs lvttl outputs delay 1 delay 1 note: 1. the enable on 7bo1/7bo2 include a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. figure 2. logic symbol
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 5 application information sw01094 thrmtrip l cpu1 ierr_l cpu1 ierr_l cpu1 thrmtrip l cpu1 prochot l forcepr_l cpu2 smi l gtl2006 56 w 56 w 1.5 k w r 2r v tt v tt v cc 10bo2 10bo1 4bi 3bi 6bi 5bi 11b0 8bo 7bo2 7bo1 2bi 1bi v cc v ref 1ao 2ao 5a 6a 11bi 11a 3ao 4ao 10ai1 10ai2 8ai gnd forcepr_l 9bi 9ao cpu2 prochot l nmi_l cpu2 ierr_l cpu2 thrmtrip l cpu1 smi l cpu2 smi l smi_buff_l v cc southbridge nmi southbridge smi_l prochot l forcepr_l prochot l thrmtrip l ierr_l platform health management 1.5 k w to 1.2 k w cpu1 smi l cpu2 optional signal line nmi nmi figure 3. application diagram
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 6 frequently asked questions question 1: on the gtl2006 lvttl inputs, specifically 10ai1 and 10ai2, when the gtl2006 is unpowered, these inputs may be pulled up to 3.3 v s/b and we want to make sure that there is no leakage path to the power rail under this condition. are the lvttl inputs high impedance when the device is unpowered and will there be any leakage? answer 1: when the device is unpowered, the lvttl inputs will be in a high-impedance state and will not leak to v dd if they are pulled high while the device is unpowered. question 2: do all the lvttl inputs have the same unpowered characteristic? answer 2: yes. question 3: what is the condition of the other gtl i/o and lvttl output pins when the device is unpowered? answer 3: the open drain outputs, both gtl and lvttl, will not leak to the power supply if they are pulled high while the device is unpowered. the gtl inputs will also not leak to the power supply under the same conditions. the lvttl totem pole outputs, however, are not open drain type outputs and there will be current flow on these pins if they are pulled high when v dd is at ground. question 4: when this sequence occurs: 1) pin 11bi is driven low (at time t0) 2) pin 11a is driven low (at time t1) 3) pin 11bi stops driving low (at time t2) 4)pin 11a stops driving low (at time t3) are there wired-or glitches at pin 11bo at time t1 and t2? answer 4: the output of 11bi is physically wired to the 11a pin. there will be no glitch at t1 when the external driver turns on and drives low, unless the external driver is a long distance away and the pull-up is a low value. if the pull-up r = z o of the line and the current were equally shared, the bounce would be to 1 / 2 the pull-up voltage, presumably v dd . the input is a 1 / 2 v dd threshold input, so the glitch may propagate to the 11bo. if the glitch is very short it may not propagate, or if the pull-up were higher the amplitude would be too small to propagate, or if the external driver were sinking more than half of the total current, it would not propagate. if the external driver is weak and a long way away you will most likely see a glitch on 11bo, because there will be a large glitch on 11a. question 5: can you give us some guideline on how high the pull-up resistor value at pin 11a needs to be to avoid glitches on 11bo? answer 5: the 11a pin is a ttl pin, generally the pull-up resistor used on ttl pins are chosen to minimize power rather than to match the line impedance. most line impedances are in the range of 50 w . if the pull-up is 3 z o , that is 150 w ; even if all the current is being sunk by the gtl2006, the initial bounce on 11a would only be 1 / 3 v dd , and would only last for the round trip time to the external driver, provided that the external driver can sink all of the current, the bounce will return low. the 1 / 3 v dd is not a high level to the gtl2006 11a pin, so no bounce would show up on the 11bo pin. normal choices for the pull-up on 11a would be in the 1 k w to several k w range, depending on speed and current considerations. question 6: please explain the timing specification of bn to bn in the ac characteristics table. which specific inputs/outputs does it cover, and why is the h > l transition so slow? answer 6: the bn to bn refers to the 4bi to 7bo1 path and to the 6bi to 7bo2 path. the times are disable and enable times since a low on 5bi or 6bi should not be reflected as a low on 7bo1 or 7bo2. the t plh corresponds to the disable time, and the t phl corresponds to the enable time. the enable time is deliberately slow to prevent glitches/false lows on the 7bon outputs, because a low on 5bi drives a low on 5a, which is an open-drain i/o and may have a slow rise time. and a low on 6bi drives a low on 6a that is an open-drain i/o that may also have a slow rise time. question 6a: now that i try to examine the circuit from the data sheet, i am just a little bit concerned. let me try to describe the function first: this circuit is used for monitoring and driving the cpu prochot#. the monitor device is a heceta7 part and its output is bi-directional, cpu1_prochot# and is connected to 5a. the cpu has an output called prochot#, which goes to 5bi and an input call frcprochot# that comes from 7bo1. when the cpu is generating prochpt# (5bi), we do not want the cpu input frcprochot# (7bo1) to also see this signal. scenario 1: cpu driving prochot# 5bi input is high and goes low; output 5a is high and goes low following 5bi. the output 7bo should stay high. 5bi input is low and goes high; output 5a is low and goes high following 5bi. the output 7bo1 should stay high. scenario 2: heceta7 driving cpu1_prochot# 5a input is high and goes low; output 7bo1 is high and goes low following 5a. the input 5bi should stay high. 5a input is low and goes high; output 7bo1 is low and goes high following 5a. the output 5bi should stay high. now i can see the reason for the delay in the enable path so that we keep the output disabled to account for the potentially slow riser time on 5a. in my mind, there should also be a delay block shown in the path 5bi to 5a so that the 5bi h-to-l can disable the driver for 7bo1 before the signal appears on the 5a input/output, thus appearing as an input to the driver for 7bo1. have you characterized what sort of glitch you get on the 7bo1 output on an h-to-l transition on 5bi? answer 6a: the disable for 7bo1 comes directly from the internal 5bi signal, and by design it always disables the low on 7bo1 before the low on the 5bi can propagate to the 5ai/o and back to the 7bo1. question 7: can i operate the gtl2006 at v tt of 1.2 v and v ref of 0.6 v? answer 7: yes; you can operate v tt up to 3.6 v and v ref between 0.5 v to 1.8 v at any v tt to adjust the high and low noise margins to your application. you don't have to follow the gtl/gtl/gtl+ specifications. the gtl v il and v ih will be 50 mv around v ref within the range of 0.5 v to 1.8 v.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 7 absolute maximum ratings 1 in accordance with the absolute maximum system (iec 134); voltages are referenced to gnd (ground = 0 v). symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +4.6 v i ik dc input diode current v i < 0 v 50 ma v dc in p ut voltage 3 a port (lvttl) 0.5 to +4.6 v v i dc inp u t v oltage 3 b port(gtl) 0.5 to +4.6 v i ok dc output diode current v o < 0 v 50 ma v o dc out p ut voltage 3 output in off or high state; a port 0.5 to +4.6 v v o dc o u tp u t v oltage 3 output in off or high state; b port 0.5 to +4.6 v i o current into any out p ut in the low state a port 32 ma i ol c u rrent into an y o u tp u t in the low state b port 30 ma i oh current into any output in the high state a port 32 ma t stg storage temperature range 60 to +150 c t j(max) maximum junction temperature +125 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v gtl 0.85 0.9 0.95 v tt termination voltage gtl 1.14 1.2 1.26 v gtl+ 1.35 1.5 1.65 overall 0.5 2 / 3 v tt 1.8 v su pp ly voltage gtl 0.5 0.6 0.63 v v ref s u ppl y v oltage gtl 0.76 0.8 0.84 v gtl+ 0.87 1.0 1.10 v in p ut voltage a port 0 3.3 3.6 v v i inp u t v oltage b port 0 v tt 3.6 v v high level in p ut voltage a port 2 e e v v ih high - le v el inp u t v oltage b port v ref + 50 mv e e v v low level in p ut voltage a port e e 0.8 v v il low - le v el inp u t v oltage b port e e v ref 50 mv v i oh high-level output current a port e e 16 ma i o low level out p ut current a port e e 16 ma i ol low - le v el o u tp u t c u rrent b port e e 15 ma t amb operating free-air temperature range 40 e 85 c
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 8 dc electrical characteristics over recommended operating conditions. voltages are referenced to gnd (ground = 0 v). limits symbol parameter test conditions 40 c to +85 c unit min typ 1 max v o a p ort v cc = 3.0 v to 3.6 v ; i oh = 100 m a v cc 0.2 e e v v oh a port v cc = 3.0 v ; i oh = 16 ma 2.1 e e v v o a port v cc = 3.0 v ; i ol = 16 ma e e 0.8 v v ol b port v cc = 3.0 v ; i ol = 15 ma e e 0.4 v a p ort v cc = 3.6 v; v i = v cc e e 1 i i a port v cc = 3.6 v; v i = 0 v e e 1 m a b port v cc = 3.6 v; v i = v tt or gnd e e 1 i cc a or b port v cc = 3.6 v;v i = v cc or gnd; i o = 0 ma e e 12 ma d i cc 3 a port or control inputs v cc = 3.6 v; v i = v cc 0.6 v e e 500 m a c o a port v o = 3.0 v or 0 v e 7.8 e p f c io b port v o = v tt or 0 v e 4.5 e pf notes: 1. all typical values are measured at v cc = 3.3 v and t amb = 25 c. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. this is the increase in supply current for each input that is at the specified lvttl voltage level rather than v cc or gnd . ac characteristics (3.3 v 0.3 v range) limits (gtl) limits (gtl) limits (gtl+) symbol parameter waveform v cc = 3.3 v 0.3 v v ref = 0.6 v v cc = 3.3 v 0.3 v v ref = 0.8 v v cc = 3.3 v 0.3 v v ref = 1.0 v unit min typ 1 max min typ 1 max min typ 1 max t plh t phl an to bn 1 2 2 4 5.5 8 10 2 2 4 5.5 8 10 2 2 4 5.5 8 10 ns t plh t phl bn to an 2 2 2 5.5 5.5 10 10 2 2 5.5 5.5 10 10 2 2 5.5 5.5 10 10 ns t plh t phl 9bi to 10bon 2 2 6 6 11 11 2 2 6 6 11 11 2 2 6 6 11 11 ns t plh t phl 2 11bi to 11bo 2 2 8 14 13 21 2 2 8 14 13 21 2 2 8 14 13 21 ns t plz t pzh bn to an (i/o) 3 2 2 5 5 10 10 2 2 5 5 10 10 2 2 5 5 10 10 ns t plh t phl bn to bn 3 4 120 7 205 11 350 4 120 7 205 11 350 4 120 7 205 11 350 ns notes: 1. all typical values are at v cc = 3.3 v and t amb = 25 c. 2. includes ~ 7.6 ns rc rise time of test load pull-up on 11a, 1.5 k w pull-up and 21 pf load on 11a has about 23 ns rc rise time.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 9 ac waveforms v m = 1.5 v at v cc 3.0 v for a ports; v m = v ref for b ports input 1.5 v output t plh t phl 1.5 v v ref v ref 3.0 v 0 v v oh v ol sw01093 voltage waveforms propagation delay times a port to b port t pulse v m v m v h 0 v voltage waveforms pulse duration v m = 1.5 v for a port and v ref for b port v h = 3 v for a port and v tt for b port waveform 1. input v ref output t plh t phl v ref 1.5 v 1.5 v v tt 0 v v oh v ol sw00469 prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. waveform 2. input t pzl t plz 3.5 v v ol + 0.3 v sw02235 1.5 v 1.5 v 1.5 v 0 v 3 v output waveform 3.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 10 performance curves 1100 400 500 600 700 800 900 1000 vth+ and vth (mv) v ref (v) 0.5 0.7 0.8 0.9 1.0 0.6 1100 400 500 600 700 800 900 1000 vth+ and vth (mv) v ref (v) 0.5 0.7 0.8 0.9 1.0 0.6 1100 400 500 600 700 800 900 1000 vth+ and vth (mv) v ref (v) 0.5 0.7 0.8 0.9 1.0 0.6 sw02255 v cc = 3.0 v t amb = 40 c v ref (mv) vth+ vth v cc = 3.3 v t amb = +25 c v ref (mv) vth+ vth v cc = 3.6 v t amb = +85 c v ref (mv) vth+ vth figure 4. gtl v th+ and v th versus v ref
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 11 test circuit pulse generator r t v i d.u.t. v o c l v cc test circuit for switching times definitions r l = load resistor c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to z out of pulse generators. 50 pf r l = 500 w sw00471 figure 5. load circuitry for a outputs pulse generator r t v i d.u.t. v o c l v cc test circuit for open drain lvttl i/o definitions r l = load resistor c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to z out of pulse generators. 50 pf r l = 500 w sw02067 2 v cc r l = 500 w figure 6. load circuitry for open drain lvttl i/o pulse generator r t v i d.u.t. v o c l v cc 50 w 30 pf v tt sw02066 figure 7. load circuit for b outputs
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 12 tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 13 revision history rev date description _2 20040621 product data (9397 750 13063). supersedes data of 2003 dec 18. modifications: ? all figures numbered. ? figure 2, alogic symbolo modified. ? page 6, frequently asked questions: add questions/answers 4, 5, 6, 6a, and 7. ? page 8, ac characteristics (3.3 v 0.3 range); t phl an to bn, gtl+ maximum: change from `1. ns' to `10 ns'. ? add aperformance curveso section on page 10. _1 20031218 product data (9397 750 12562); ecn 853-2440 01-a14985 dated 15 december 2003.
philips semiconductors product data gtl2006 13-bit gtl/gtl/gtl+ to lvttl translator 2004 jun 21 14 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 06-04 document order number: 9397 750 13063 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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